1. Field of the Invention
This invention is related to the field of processors and, more particularly, to setting mode indications in a processor architecture.
2. Description of the Related Art
Processor architectures often provide a variety of modes, typically programmable in configuration registers and/or memory locations read by the processor during operation. The selected mode generally controls the operation of certain aspects of the processor, as defined by the processor architecture. Other modes may cause different operation in those aspects.
As the processor architecture evolves, it may be desirable to add new modes. Sometimes, as these new modes are added, it is difficult to reliably establish the mode during operation of a processor implementing the architecture. The difficulty may arise from interactions between the mode and other, previously defined modes, or may arise from a different definition of the previously defined modes when the newly defined mode is established. As the processor is transitioned from one mode to another, it is frequently necessary to minimize the activity occurring in the processor to eliminate undefined states from occurring as the mode change takes effect.
Unfortunately, in some circumstances, it may be impossible to eliminate the undefined states. In such cases, the newly defined mode may not be implementable (limiting the ability of the processor architecture to be extended), or one of the previously defined modes may have to be changed or eliminated (which may reduce compatibility with previous processors which implemented the architecture). Also, many of the combinations of the newly defined mode and the previously defined modes may not be useful, but supporting all of the combinations may complicate implementation of the processor architecture. Complicating the implementation merely to allow all combinations of newly defined modes and previously defined modes is undesirable.